What is RISC-V?

RISC-V is an instruction set architecture, or ISA — what you could call a “blueprint” for running code on a computer processor. RISC-V is best understood in contrast to the two predominant ISAs currently on the market, x86 and ARM, names you may have heard before. But what makes RISC-V notable? Two things: It’s open source, and it’s a (relatively) new entrant in a space with very little active competition.

RISC-V Processor vs RISC-V ISA

A RISC-V processor is a computer chip that is designed to execute code using the RISC-V ISA.

One core concept to understand in relation to RISC-V is the difference between a computer processor and an ISA (instruction set architecture). A computer processor is the physical piece of hardware — the actual microchip running the code that powers the applications on a computer. The ISA defines the particular type of code that the processor is designed to run (again, a sort of “blueprint”) and, therefore, to some extent, the design of that processor. 

In practice, we describe families of computer processors by their native instruction set architecture (e.g., an Intel or AMD processor uses the x86 ISA, but we often just talk about Intel or AMD chips as being “x86 processors”).

RISC-V History

In many ways, RISC-V is a product of the x86 monopoly and its subsequent disruption by ARM. For years, Intel’s dominant x86 processor architecture precluded any competing instruction set from gaining a substantial foothold in the marketplace. Apple was one of the last non-x86 consumer computer holdouts with its IBM-derived PowerPC architecture, but it signed an agreement with Intel to power its Mac computers with x86 chips starting in 2005 (Apple has since left x86 behind again, moving to its own ARM-based Apple Silicon processors). Around this time, though, a new computing form factor was exploding in popularity: The mobile phone. And x86 wasn’t the ISA powering that revolution.

The ARM instruction set is used by virtually every smartphone and wearable device on the planet. The ARM instruction set was developed beginning in the 1980s but didn’t achieve major commercial success until mobile phones launched it into relevance globally. However, ARM is a proprietary ISA and microprocessor architecture developed and owned by Arm Holdings, and manufacturers of ARM processors must be ARM licensees (and thus, pay royalties). ARM’s success was a massive disruption to Intel and x86, one that continues to this day.

While Arm Holdings offers a more open licensing model whereby any vendor can pay to license and iterate on Arm’s silicon reference designs (Intel rarely licenses x86 to anyone), those designs must adhere to the ARM ISA, which is defined by Arm — and is not open source. This means that, when all is said and done, Arm Holdings, a private company, still decides the evolution and priorities of the ARM architecture and controls its distribution. RISC-V is, in some sense, a natural next step: From the closed ecosystem of x86, to the partner-enabled ARM ecosystem, to a truly open source model for an ISA with RISC-V.

In 2010, the first iteration of RISC-V was built by a group at the University of California Berkeley. From the start, this new ISA was meant to be an open source initiative, though the scope of its ambition was quite a bit narrower than it has become. Over the years and through several iterations, interest in RISC-V grew substantially. The reason? Well, contributors would likely say it’s a well-designed ISA designed for a high degree of flexibility, which may well be true. But because RISC-V is open source, there are no license fees to use it. RISC-V licensees simply must remain compatible with the base instruction set if they wish to use the RISC-V name. And if they don’t want to use the RISC-V name, they can do whatever they want with it — including building incompatible forks of the instruction set.

What RISC-V Devices Exist?

There are very few publicly disclosed implementations of RISC-V in commercial products, aside from development boards. One of the only known examples is Google’s Titan M2 security chip, included on its Pixel Android smartphones. Allegedly, a RISC-V laptop by Framework will ship soon. Still, there are claims by the RISC-V Organization that over 10 billion RISC-V cores have shipped worldwide, meaning that the demand for the RISC-V ISA is growing. It’s just not totally clear where that demand stems from.

Right now, development of RISC-V based devices is happening almost entirely behind closed doors. And it’s possible that much of that development is occurring on non-RISC-V hardware, instead using virtualization to run the RISC-V ISA on other types of processors like FPGAs. Because the RISC-V ISA is open source, it is possible for an interested entity — say, a state-level actor, defense contractor, or major corporation — to utilize the RISC-V ISA for the purpose of building an entirely closed-source project, without any need to obtain licenses or other permission. Similarly, such groups could “fork” the ISA over time and make it incompatible with “true” RISC-V systems for their own specific purposes.

This is all to say: There are certainly motives to build RISC-V devices. A truly open-source instruction set architecture opens up possibilities for custom silicon implementations and functionality that ISAs like x86 and ARM may not be suited to provide. RISC-V also is one of the only ISAs for anyone who cannot easily obtain ARM and x86 licenses in the first place — use your imagination as to who that might be.

RISC-V vs ARM and x86

RISC-V’s major benefit over ARM and x86 ISAs is that RISC-V is an open source technology. Compared to x86, both ARM and RISC-V are “Reduced Instruction Set Computer” type architectures, though the two don’t share a specific technical lineage. Rather, both are born of the concept of a reduced instruction set computer. X86, by comparison, is a CISC architecture (Complex Instruction Set Computer).

The primary differences in practice between the three relate to their relative popularity and respective business models.

ARM processors are found in smartphones, tablets, IoT and edge devices, and many other devices all over the planet. x86 processors are common in desktop and laptop computers, servers, and enterprise computing infrastructure. ARM blew past even x86 on a pure volume shipment basis long ago, and the number of ARM chipsets fabricated per year is now an order of magnitude greater than x86. ARM is, therefore, far and away the most dominant processor ISA in existence. RISC-V, by comparison, holds so little market share that it’s not been possible to meaningfully quantify. No real RISC-V commercial ecosystem yet exists — though that’s not to say it won’t in the near future.

The relatively low popularity of RISC-V processors compared to ARM and x86 processors means that very little software is currently available to run on RISC-V systems (without the use of emulation). And there is effectively no consumer-grade software for RISC-V at all. Notably, operating system support for RISC-V is growing — Android is now RISC-V compatible, as are a number of popular Linux distributions. But the hardware available to run these OSes exists largely in the form of development boards designed for hobbyists and professionals.

The other major difference between RISC-V, ARM, and x86 are their commercial models. Arm Holdings is a privately-held company that licenses the closed source ARM ISA to partners who wish to use it, but this comes at a significant royalty cost, as well as agreements to maintain technical compatibility. x86 is owned by Intel, and only licensed to a very select few other entities (such as AMD). Intel generally doesn’t partner as a means to grow the x86 ISA footprint, instead preferring to own the “full stack” of technologies and sell chips on its own. RISC-V is an open source ISA that is available to anyone, making it quite unusual in the ISA space. The RISC-V Organization defines the RISC-V ISA, and members of the organization contribute to its ongoing development and can use the RISC-V trademark to advertise the compatibility of their products. Non-members, though, can still use the RISC-V open source code as they like under the ISA’s permissive license, even if they want to break compatibility with the ISA.

The Future of RISC-V

Right now, it’s difficult to say where RISC-V is headed. ARM’s dominance in the mobile space seems well established, though if RISC-V could offer similar performance at a lower cost one day thanks to its open source model, who knows what could happen? But it’s still far too early to tell where RISC-V will find the most utility. The appeal of RISC-V is potentially broad, but the specific economics of implementation aren’t clear enough yet to say confidently where it might establish that first major foothold. Much of RISC-V’s adoption also won’t happen in public, at least initially. Closed source, internal projects — by companies and other organizations building devices and platforms for their own systems and infrastructure — have no reason to disclose their use of RISC-V. For now, RISC-V remains a very interesting and young upstart in a space dominated by incumbents that are many decades old. Its ability to disrupt them has yet to prove out.